Attachment 371485 Details for Bug 198604 – Patch

[patch] Patch

refactor-reginfo.patch (text/plain), 54.83 KB, created by Paulo Matos on 2019-06-06 03:34:25 PDT

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Creator: Paulo Matos

Created: 2019-06-06 03:34:25 PDT

Size: 54.83 KB

patch

obsolete

>commit 8b032eabb038e543bc77f891f6afed2542a00299
>Author: Paulo Matos <pmatos@linki.tools>
>Date:   Wed May 8 18:36:44 2019 +0200
>
>    Prototype for register information aggregation.
>    
>    This prototype works for ARM64, ARMv7, MIPS, X86 and X86_64,
>    which are all the supported architectures.
>    
>    <arch>Registers.h are specification files that describe available
>    registers and their properties on each architecture.
>
>diff --git a/Source/JavaScriptCore/assembler/ARM64Assembler.h b/Source/JavaScriptCore/assembler/ARM64Assembler.h
>index 6fd628a2586..d25fb2afbb9 100644
>--- a/Source/JavaScriptCore/assembler/ARM64Assembler.h
>+++ b/Source/JavaScriptCore/assembler/ARM64Assembler.h
>@@ -31,6 +31,7 @@
> #include "AssemblerCommon.h"
> #include "CPU.h"
> #include "JSCPtrTag.h"
>+#include "ARM64Registers.h"
> #include <limits.h>
> #include <wtf/Assertions.h>
> #include <wtf/Vector.h>
>@@ -164,103 +165,36 @@ inline uint16_t getHalfword(uint64_t value, int which)
>     return value >> (which << 4);
> }
> 
>+// If modifying the namespace name, please be sure to modify it as well
>+//   in ARM64Registers.h on the macro definition of REGNS 
> namespace ARM64Registers {
> 
> typedef enum : int8_t {
>-    // Parameter/result registers.
>-    x0,
>-    x1,
>-    x2,
>-    x3,
>-    x4,
>-    x5,
>-    x6,
>-    x7,
>-    // Indirect result location register.
>-    x8,
>-    // Temporary registers.
>-    x9,
>-    x10,
>-    x11,
>-    x12,
>-    x13,
>-    x14,
>-    x15,
>-    // Intra-procedure-call scratch registers (temporary).
>-    x16,
>-    x17,
>-    // Platform Register (temporary).
>-    x18,
>-    // Callee-saved.
>-    x19,
>-    x20,
>-    x21,
>-    x22,
>-    x23,
>-    x24,
>-    x25,
>-    x26,
>-    x27,
>-    x28,
>-    // Special.
>-    fp,
>-    lr,
>-    sp,
>-
>-    ip0 = x16,
>-    ip1 = x17,
>-    x29 = fp,
>-    x30 = lr,
>-    zr = 0x3f,
>+#define REGID(id, nsid, name, r, cs) id,
>+    FOR_EACH_GP_REGISTER(REGID)
>+#undef REGID                   
>+                       
>+#define REGALIAS(id, nsid, name, alias) id = alias,
>+    FOR_EACH_REGISTER_ALIAS(REGALIAS)
>+#undef REGALIAS
>+
>     InvalidGPRReg = -1,
> } RegisterID;
> 
> typedef enum : int8_t {
>-    pc,
>-    nzcv,
>-    fpsr
>+#define REGID(id, nsid, name) id,
>+    FOR_EACH_SP_REGISTER(REGID)
>+#undef REGID
> } SPRegisterID;
> 
> // ARM64 always has 32 FPU registers 128-bits each. See http://llvm.org/devmtg/2012-11/Northover-AArch64.pdf
> // and Section 5.1.2 in http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.pdf.
> // However, we only use them for 64-bit doubles.
> typedef enum : int8_t {
>-    // Parameter/result registers.
>-    q0,
>-    q1,
>-    q2,
>-    q3,
>-    q4,
>-    q5,
>-    q6,
>-    q7,
>-    // Callee-saved (up to 64-bits only!).
>-    q8,
>-    q9,
>-    q10,
>-    q11,
>-    q12,
>-    q13,
>-    q14,
>-    q15,
>-    // Temporary registers.
>-    q16,
>-    q17,
>-    q18,
>-    q19,
>-    q20,
>-    q21,
>-    q22,
>-    q23,
>-    q24,
>-    q25,
>-    q26,
>-    q27,
>-    q28,
>-    q29,
>-    q30,
>-    q31,
>-    InvalidFPRReg = -1,
>+#define REGID(id, nsid, name, r, cs) id,
>+    FOR_EACH_FP_REGISTER(REGID)
>+#undef REGID                       
>+       InvalidFPRReg = -1,
> } FPRegisterID;
> 
> static constexpr bool isSp(RegisterID reg) { return reg == sp; }
>@@ -292,10 +226,9 @@ public:
>     {
>         ASSERT(id >= firstRegister() && id <= lastRegister());
>         static const char* const nameForRegister[numberOfRegisters()] = {
>-            "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
>-            "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
>-            "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
>-            "r24", "r25", "r26", "r27", "r28", "fp", "lr", "sp"
>+#define REGNAME(id, nsid, name, r, cs) name,
>+        FOR_EACH_GP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>@@ -304,7 +237,9 @@ public:
>     {
>         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
>         static const char* const nameForRegister[numberOfSPRegisters()] = {
>-            "pc", "nzcv", "fpsr"
>+#define REGNAME(id, nsid, name) name,
>+        FOR_EACH_SP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>@@ -313,10 +248,9 @@ public:
>     {
>         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
>         static const char* const nameForRegister[numberOfFPRegisters()] = {
>-            "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
>-            "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15",
>-            "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23",
>-            "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31"
>+#define REGNAME(id, nsid, name, r, cs) name,
>+        FOR_EACH_FP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>diff --git a/Source/JavaScriptCore/assembler/ARM64Registers.h b/Source/JavaScriptCore/assembler/ARM64Registers.h
>new file mode 100644
>index 00000000000..a3a79724cad
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/ARM64Registers.h
>@@ -0,0 +1,174 @@
>+/*
>+ * Copyright (C) 2019 Metrological Group B.V.
>+ * Copyright (C) 2019 Igalia S.L.
>+ *
>+ * Redistribution and use in source and binary forms, with or without
>+ * modification, are permitted provided that the following conditions
>+ * are met:
>+ * 1. Redistributions of source code must retain the above copyright
>+ *    notice, this list of conditions and the following disclaimer.
>+ * 2. Redistributions in binary form must reproduce the above copyright
>+ *    notice, this list of conditions and the following disclaimer in the
>+ *    documentation and/or other materials provided with the distribution.
>+ *
>+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
>+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
>+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
>+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
>+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
>+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>+ */
>+
>+#pragma once
>+
>+#define REGNS ARM64Registers
>+#define n(id) id, REGNS::id, #id
>+
>+#define FOR_EACH_REGISTER(macro)                \
>+    FOR_EACH_GP_REGISTER(macro)                 \
>+    FOR_EACH_FP_REGISTER(macro)
>+
>+#define macro(m, ...) m(__VA_ARGS__)
>+
>+// We don't include LR in the set of callee-save registers even though it technically belongs
>+// there. This is because we use this set to describe the set of registers that need to be saved
>+// beyond what you would save by the platform-agnostic "preserve return address" and "restore
>+// return address" operations in CCallHelpers.
>+
>+#if !PLATFORM(IOS_FAMILY)
>+#define FOR_EACH_GP_REGISTER(m)                                 \
>+    /* Parameter/result registers. */                           \
>+    macro(m, n(x0), 0, 0)                                       \
>+    macro(m, n(x1), 0, 0)                                       \
>+    macro(m, n(x2), 0, 0)                                       \
>+    macro(m, n(x3), 0, 0)                                       \
>+    macro(m, n(x4), 0, 0)                                       \
>+    macro(m, n(x5), 0, 0)                                       \
>+    macro(m, n(x6), 0, 0)                                       \
>+    macro(m, n(x7), 0, 0)                                       \
>+    /* Indirect result location register. */                    \
>+    macro(m, n(x8), 0, 0)                                       \
>+    /* Temporary registers. */                                  \
>+    macro(m, n(x9), 0, 0)                                       \
>+    macro(m, n(x10), 0, 0)                                      \
>+    macro(m, n(x11), 0, 0)                                      \
>+    macro(m, n(x12), 0, 0)                                      \
>+    macro(m, n(x13), 0, 0)                                      \
>+    macro(m, n(x14), 0, 0)                                      \
>+    macro(m, n(x15), 0, 0)                                      \
>+    /* Intra-procedure-call scratch registers (temporary). */   \
>+    macro(m, n(x16), 0, 0)                                      \
>+    macro(m, n(x17), 0, 0)                                      \
>+    /* Platform Register (temporary). */                        \
>+    macro(m, n(x18), 0, 0)                                      \
>+    /* Callee-saved. */                                         \
>+    macro(m, n(x19), 0, 1)                                      \
>+    macro(m, n(x20), 0, 1)                                      \
>+    macro(m, n(x21), 0, 1)                                      \
>+    macro(m, n(x22), 0, 1)                                      \
>+    macro(m, n(x23), 0, 1)                                      \
>+    macro(m, n(x24), 0, 1)                                      \
>+    macro(m, n(x25), 0, 1)                                      \
>+    macro(m, n(x26), 0, 1)                                      \
>+    macro(m, n(x27), 0, 1)                                      \
>+    macro(m, n(x28), 0, 1)                                      \
>+    /* Special. */                                              \
>+    macro(m, n(fp), 0, 1)                                       \
>+    macro(m, n(lr), 1, 0)                                       \
>+    macro(m, n(sp), 0, 0)
>+#else
>+#define FOR_EACH_GP_REGISTER(macro)                             \
>+    /* Parameter/result registers. */                           \
>+    macro(m, n(x0), 0, 0)                                       \
>+    macro(m, n(x1), 0, 0)                                       \
>+    macro(m, n(x2), 0, 0)                                       \
>+    macro(m, n(x3), 0, 0)                                       \
>+    macro(m, n(x4), 0, 0)                                       \
>+    macro(m, n(x5), 0, 0)                                       \
>+    macro(m, n(x6), 0, 0)                                       \
>+    macro(m, n(x7), 0, 0)                                       \
>+    /* Indirect result location register. */                    \
>+    macro(m, n(x8), 0, 0)                                       \
>+    /* Temporary registers. */                                  \
>+    macro(m, n(x9), 0, 0)                                       \
>+    macro(m, n(x10), 0, 0)                                      \
>+    macro(m, n(x11), 0, 0)                                      \
>+    macro(m, n(x12), 0, 0)                                      \
>+    macro(m, n(x13), 0, 0)                                      \
>+    macro(m, n(x14), 0, 0)                                      \
>+    macro(m, n(x15), 0, 0)                                      \
>+    /* Intra-procedure-call scratch registers (temporary). */   \
>+    macro(m, n(x16), 0, 0)                                      \
>+    macro(m, n(x17), 0, 0)                                      \
>+    /* Platform Register (temporary). */                        \
>+    macro(m, n(x18), 1, 0)                                      \
>+    /* Callee-saved. */                                         \
>+    macro(m, n(x19), 0, 1)                                      \
>+    macro(m, n(x20), 0, 1)                                      \
>+    macro(m, n(x21), 0, 1)                                      \
>+    macro(m, n(x22), 0, 1)                                      \
>+    macro(m, n(x23), 0, 1)                                      \
>+    macro(m, n(x24), 0, 1)                                      \
>+    macro(m, n(x25), 0, 1)                                      \
>+    macro(m, n(x26), 0, 1)                                      \
>+    macro(m, n(x27), 0, 1)                                      \
>+    macro(m, n(x28), 0, 1)                                      \
>+    /* Special. */                                              \
>+    macro(m, n(fp), 0, 1)                                       \
>+    macro(m, n(lr), 1, 0)                                       \
>+    macro(m, n(sp), 0, 0)
>+#endif
>+
>+#define FOR_EACH_REGISTER_ALIAS(m)                 \
>+    macro(m, n(ip0), x16)                          \
>+    macro(m, n(ip1), x17)                          \
>+    macro(m, n(x29), fp)                           \
>+    macro(m, n(x30), lr)                           \
>+    macro(m, n(zr), 0x3f)
>+
>+#define FOR_EACH_SP_REGISTER(m)                   \
>+    macro(m, n(pc))                               \
>+    macro(m, n(nzcv))                             \
>+    macro(m, n(fpsr))
>+
>+#define FOR_EACH_FP_REGISTER(m)                 \
>+    /* Parameter/result registers. */           \
>+    macro(m, n(q0), 0, 0)                       \
>+    macro(m, n(q1), 0, 0)                       \
>+    macro(m, n(q2), 0, 0)                       \
>+    macro(m, n(q3), 0, 0)                       \
>+    macro(m, n(q4), 0, 0)                       \
>+    macro(m, n(q5), 0, 0)                       \
>+    macro(m, n(q6), 0, 0)                       \
>+    macro(m, n(q7), 0, 0)                       \
>+    /* Callee-saved (up to 64-bits only!). */   \
>+    macro(m, n(q8), 0, 1)                       \
>+    macro(m, n(q9), 0, 1)                       \
>+    macro(m, n(q10), 0, 1)                      \
>+    macro(m, n(q11), 0, 1)                      \
>+    macro(m, n(q12), 0, 1)                      \
>+    macro(m, n(q13), 0, 1)                      \
>+    macro(m, n(q14), 0, 1)                      \
>+    macro(m, n(q15), 0, 1)                      \
>+    /* Temporary registers. */                  \
>+    macro(m, n(q16), 0, 0)                      \
>+    macro(m, n(q17), 0, 0)                      \
>+    macro(m, n(q18), 0, 0)                      \
>+    macro(m, n(q19), 0, 0)                      \
>+    macro(m, n(q20), 0, 0)                      \
>+    macro(m, n(q21), 0, 0)                      \
>+    macro(m, n(q22), 0, 0)                      \
>+    macro(m, n(q23), 0, 0)                      \
>+    macro(m, n(q24), 0, 0)                      \
>+    macro(m, n(q25), 0, 0)                      \
>+    macro(m, n(q26), 0, 0)                      \
>+    macro(m, n(q27), 0, 0)                      \
>+    macro(m, n(q28), 0, 0)                      \
>+    macro(m, n(q29), 0, 0)                      \
>+    macro(m, n(q30), 0, 0)                      \
>+    macro(m, n(q31), 0, 0)
>diff --git a/Source/JavaScriptCore/assembler/ARMv7Assembler.h b/Source/JavaScriptCore/assembler/ARMv7Assembler.h
>index 6fe04e44623..42f150dd908 100644
>--- a/Source/JavaScriptCore/assembler/ARMv7Assembler.h
>+++ b/Source/JavaScriptCore/assembler/ARMv7Assembler.h
>@@ -30,6 +30,7 @@
> 
> #include "AssemblerBuffer.h"
> #include "AssemblerCommon.h"
>+#include "ARMv7Registers.h"
> #include <limits.h>
> #include <wtf/Assertions.h>
> #include <wtf/Vector.h>
>@@ -37,132 +38,45 @@
> 
> namespace JSC {
> 
>+// If modifying the namespace name, please be sure to modify it as well
>+//   in ARMv7Registers.h on the macro definition of REGNS 
> namespace ARMRegisters {
> 
>     typedef enum : int8_t {
>-        r0,
>-        r1,
>-        r2,
>-        r3,
>-        r4,
>-        r5,
>-        r6,
>-        r7,
>-        r8,
>-        r9,
>-        r10,
>-        r11,
>-        r12,
>-        r13,
>-        r14,
>-        r15,
>-
>-        fp = r7,   // frame pointer
>-        sb = r9,   // static base
>-        sl = r10,  // stack limit
>-        ip = r12,
>-        sp = r13,
>-        lr = r14,
>-        pc = r15,
>+#define REGID(id, name, r, cs) id,
>+        FOR_EACH_GP_REGISTER(REGID)
>+#undef REGID
>+
>+#define REGALIAS(id, name, alias) id = alias,
>+        FOR_EACH_REGISTER_ALIAS(REGALIAS)
>+#undef REGALIAS
>         InvalidGPRReg = -1,
>     } RegisterID;
> 
>     typedef enum : int8_t {
>-        apsr,
>-        fpscr
>+#define REGID(id, name) id,
>+        FOR_EACH_SP_REGISTER(REGID)
>+#undef REGID
>     } SPRegisterID;
> 
>     typedef enum : int8_t {
>-        s0,
>-        s1,
>-        s2,
>-        s3,
>-        s4,
>-        s5,
>-        s6,
>-        s7,
>-        s8,
>-        s9,
>-        s10,
>-        s11,
>-        s12,
>-        s13,
>-        s14,
>-        s15,
>-        s16,
>-        s17,
>-        s18,
>-        s19,
>-        s20,
>-        s21,
>-        s22,
>-        s23,
>-        s24,
>-        s25,
>-        s26,
>-        s27,
>-        s28,
>-        s29,
>-        s30,
>-        s31,
>+#define REGID(id, name) id,
>+        FOR_EACH_FP_REGISTER(REGID)
>+#undef REGID
>     } FPSingleRegisterID;
> 
>     typedef enum : int8_t {
>-        d0,
>-        d1,
>-        d2,
>-        d3,
>-        d4,
>-        d5,
>-        d6,
>-        d7,
>-        d8,
>-        d9,
>-        d10,
>-        d11,
>-        d12,
>-        d13,
>-        d14,
>-        d15,
>-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
>-        d16,
>-        d17,
>-        d18,
>-        d19,
>-        d20,
>-        d21,
>-        d22,
>-        d23,
>-        d24,
>-        d25,
>-        d26,
>-        d27,
>-        d28,
>-        d29,
>-        d30,
>-        d31,
>-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
>+#define REGID(id, name) id,
>+        FOR_EACH_DOUBLE_FP_REGISTER(REGID)
>+#undef REGID
>         InvalidFPRReg = -1,
>     } FPDoubleRegisterID;
> 
> #if CPU(ARM_NEON)
>     typedef enum : int8_t {
>-        q0,
>-        q1,
>-        q2,
>-        q3,
>-        q4,
>-        q5,
>-        q6,
>-        q7,
>-        q8,
>-        q9,
>-        q10,
>-        q11,
>-        q12,
>-        q13,
>-        q14,
>-        q15,
>+#define REGID(id, name) id,
>+        FOR_EACH_QUAD_FP_REGISTER(REGID)
>+#undef REGID
>     } FPQuadRegisterID;
> #endif // CPU(ARM_NEON)
> 
>@@ -455,10 +369,9 @@ public:
>     {
>         ASSERT(id >= firstRegister() && id <= lastRegister());
>         static const char* const nameForRegister[numberOfRegisters()] = {
>-            "r0", "r1", "r2", "r3",
>-            "r4", "r5", "r6", "fp",
>-            "r8", "r9", "r10", "r11",
>-            "ip", "sp", "lr", "pc"
>+#define REGNAME(id, name, r, s) name,
>+        FOR_EACH_GP_DOUBLE_REGISTER(REGNAME)
>+#undef REGNAME        
>         };
>         return nameForRegister[id];
>     }
>@@ -467,7 +380,9 @@ public:
>     {
>         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
>         static const char* const nameForRegister[numberOfSPRegisters()] = {
>-            "apsr", "fpscr"
>+#define REGNAME(id, name) name,
>+        FOR_EACH_SP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>@@ -476,16 +391,9 @@ public:
>     {
>         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
>         static const char* const nameForRegister[numberOfFPRegisters()] = {
>-            "d0", "d1", "d2", "d3",
>-            "d4", "d5", "d6", "d7",
>-            "d8", "d9", "d10", "d11",
>-            "d12", "d13", "d14", "d15",
>-#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
>-            "d16", "d17", "d18", "d19",
>-            "d20", "d21", "d22", "d23",
>-            "d24", "d25", "d26", "d27",
>-            "d28", "d29", "d30", "d31"
>-#endif // CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
>+#define REGNAME(id, name) name,
>+        FOR_EACH_FP_DOUBLE_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>diff --git a/Source/JavaScriptCore/assembler/ARMv7Registers.h b/Source/JavaScriptCore/assembler/ARMv7Registers.h
>new file mode 100644
>index 00000000000..156dc773a27
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/ARMv7Registers.h
>@@ -0,0 +1,197 @@
>+/*
>+ * Copyright (C) 2019 Metrological Group B.V.
>+ * Copyright (C) 2019 Igalia S.L.
>+ * 
>+ * Redistribution and use in source and binary forms, with or without
>+ * modification, are permitted provided that the following conditions
>+ * are met:
>+ * 1. Redistributions of source code must retain the above copyright
>+ *    notice, this list of conditions and the following disclaimer.
>+ * 2. Redistributions in binary form must reproduce the above copyright
>+ *    notice, this list of conditions and the following disclaimer in the
>+ *    documentation and/or other materials provided with the distribution.
>+ *
>+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
>+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
>+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
>+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
>+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
>+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
>+ */
>+
>+
>+#pragma once
>+
>+#define REGNS ARMRegisters
>+#define n(id) id, #id, REGNS::id
>+
>+#define FOR_EACH_REGISTER(macro)                \
>+    FOR_EACH_GP_REGISTER(macro)                 \
>+    FOR_EACH_SP_REGISTER(macro)                 \
>+    FOR_EACH_FP_SINGLE_REGISTER(macro)          \
>+    FOR_EACH_FP_DOUBLE_REGISTER(macro)          \
>+    FOR_EACH_FP_QUAD_REGISTER(macro)
>+
>+#if !PLATFORM(IOS_FAMILY)
>+#define FOR_EACH_GP_REGISTER(macro)             \
>+    macro(n(r0), 0, 0)                          \
>+    macro(n(r1), 0, 0)                          \
>+    macro(n(r2), 0, 0)                          \
>+    macro(n(r3), 0, 0)                          \
>+    macro(n(r4), 0, 1)                          \
>+    macro(n(r5), 0, 1)                          \
>+    macro(n(r6), 0, 1)                          \
>+    macro(n(r7), 0, 0)                          \
>+    macro(n(r8), 0, 1)                          \
>+    macro(n(r9), 0, 1)                          \
>+    macro(n(r10), 0, 1)                         \
>+    macro(n(r11), 0, 1)                         \
>+    macro(r12, "ip", 0, 0)                      \
>+    macro(r13, "sp", 0, 0)                      \
>+    macro(r14, "lr", 1, 0)                      \
>+    macro(r15, "pc", 1, 0)
>+#else
>+#define FOR_EACH_GP_REGISTER(macro)             \
>+    macro(n(r0), 0, 0)                          \
>+    macro(n(r1), 0, 0)                          \
>+    macro(n(r2), 0, 0)                          \
>+    macro(n(r3), 0, 0)                          \
>+    macro(n(r4), 0, 1)                          \
>+    macro(n(r5), 0, 1)                          \
>+    macro(n(r6), 0, 1)                          \
>+    macro(n(r7), 0, 0)                          \
>+    macro(n(r8), 0, 1)                          \
>+    macro(n(r9), 0, 0)                          \
>+    macro(n(r10), 0, 1)                         \
>+    macro(n(r11), 0, 1)                         \
>+    macro(r12, "ip", 0, 0)                      \
>+    macro(r13, "sp", 0, 0)                      \
>+    macro(r14, "lr", 1, 0)                      \
>+    macro(r15, "pc", 1, 0)
>+#endif
>+
>+#define FOR_EACH_REGISTER_ALIAS(macro)          \
>+    macro(n(fp), r7)                            \
>+    macro(n(sb), r9)                            \
>+    macro(n(sl), r10)                           \
>+    macro(n(ip), r12)                           \
>+    macro(n(sp), r13)                           \
>+    macro(n(lr), r14)                           \
>+    macro(n(pc), r15)
>+
>+#define FOR_EACH_SP_REGISTER(macro)             \
>+    macro(n(apsr))                              \
>+    macro(n(fpscr))
>+
>+#define FOR_EACH_FP_SINGLE_REGISTER(macro)      \
>+    macro(n(s0))                                \
>+    macro(n(s1))                                \
>+    macro(n(s2))                                \
>+    macro(n(s3))                                \
>+    macro(n(s4))                                \
>+    macro(n(s5))                                \
>+    macro(n(s6))                                \
>+    macro(n(s7))                                \
>+    macro(n(s8))                                \
>+    macro(n(s9))                                \
>+    macro(n(s10))                               \
>+    macro(n(s11))                               \
>+    macro(n(s12))                               \
>+    macro(n(s13))                               \
>+    macro(n(s14))                               \
>+    macro(n(s15))                               \
>+    macro(n(s16))                               \
>+    macro(n(s17))                               \
>+    macro(n(s18))                               \
>+    macro(n(s19))                               \
>+    macro(n(s20))                               \
>+    macro(n(s21))                               \
>+    macro(n(s22))                               \
>+    macro(n(s23))                               \
>+    macro(n(s24))                               \
>+    macro(n(s25))                               \
>+    macro(n(s26))                               \
>+    macro(n(s27))                               \
>+    macro(n(s28))                               \
>+    macro(n(s29))                               \
>+    macro(n(s30))                               \
>+    macro(n(s31))
>+
>+#if CPU(ARM_NEON) || CPU(ARM_VFP_V3_D32)
>+#define FOR_EACH_FP_DOUBLE_REGISTER(macro)      \
>+    macro(n(d0))                                \
>+    macro(n(d1))                                \
>+    macro(n(d2))                                \
>+    macro(n(d3))                                \
>+    macro(n(d4))                                \
>+    macro(n(d5))                                \
>+    macro(n(d6))                                \
>+    macro(n(d7))                                \
>+    macro(n(d8))                                \
>+    macro(n(d9))                                \
>+    macro(n(d10))                               \
>+    macro(n(d11))                               \
>+    macro(n(d12))                               \
>+    macro(n(d13))                               \
>+    macro(n(d14))                               \
>+    macro(n(d15))                               \
>+    macro(n(d16))                               \
>+    macro(n(d17))                               \
>+    macro(n(d18))                               \
>+    macro(n(d19))                               \
>+    macro(n(d20))                               \
>+    macro(n(d21))                               \
>+    macro(n(d22))                               \
>+    macro(n(d23))                               \
>+    macro(n(d24))                               \
>+    macro(n(d25))                               \
>+    macro(n(d26))                               \
>+    macro(n(d27))                               \
>+    macro(n(d28))                               \
>+    macro(n(d29))                               \
>+    macro(n(d30))                               \
>+    macro(n(d31))
>+#else
>+#define FOR_EACH_FP_DOUBLE_REGISTER(macro)      \
>+    macro(n(d0))                                \
>+    macro(n(d1))                                \
>+    macro(n(d2))                                \
>+    macro(n(d3))                                \
>+    macro(n(d4))                                \
>+    macro(n(d5))                                \
>+    macro(n(d6))                                \
>+    macro(n(d7))                                \
>+    macro(n(d8))                                \
>+    macro(n(d9))                                \
>+    macro(n(d10))                               \
>+    macro(n(d11))                               \
>+    macro(n(d12))                               \
>+    macro(n(d13))                               \
>+    macro(n(d14))                               \
>+    macro(n(d15))
>+#endif
>+
>+#if CPU(ARM_NEON)
>+#define FOR_EACH_FP_QUAD_REGISTER(macro)        \
>+    macro(n(q0))                                \
>+    macro(n(q1))                                \
>+    macro(n(q2))                                \
>+    macro(n(q3))                                \
>+    macro(n(q4))                                \
>+    macro(n(q5))                                \
>+    macro(n(q6))                                \
>+    macro(n(q7))                                \
>+    macro(n(q8))                                \
>+    macro(n(q9))                                \
>+    macro(n(q10))                               \
>+    macro(n(q11))                               \
>+    macro(n(q12))                               \
>+    macro(n(q13))                               \
>+    macro(n(q14))                               \
>+    macro(n(q15))
>+#endif
>diff --git a/Source/JavaScriptCore/assembler/MIPSAssembler.h b/Source/JavaScriptCore/assembler/MIPSAssembler.h
>index 7e8e213dfce..57e08dbc42c 100644
>--- a/Source/JavaScriptCore/assembler/MIPSAssembler.h
>+++ b/Source/JavaScriptCore/assembler/MIPSAssembler.h
>@@ -35,122 +35,35 @@
> #include <limits.h>
> #include <wtf/Assertions.h>
> #include <wtf/SegmentedVector.h>
>+#include "MIPSRegisters.h"
> 
> namespace JSC {
> 
> typedef uint32_t MIPSWord;
> 
>+// If modifying the namespace name, please be sure to modify it as well
>+//   in MIPSRegisters.h on the macro definition of REGNS     
> namespace MIPSRegisters {
> typedef enum : int8_t {
>-    r0 = 0,
>-    r1,
>-    r2,
>-    r3,
>-    r4,
>-    r5,
>-    r6,
>-    r7,
>-    r8,
>-    r9,
>-    r10,
>-    r11,
>-    r12,
>-    r13,
>-    r14,
>-    r15,
>-    r16,
>-    r17,
>-    r18,
>-    r19,
>-    r20,
>-    r21,
>-    r22,
>-    r23,
>-    r24,
>-    r25,
>-    r26,
>-    r27,
>-    r28,
>-    r29,
>-    r30,
>-    r31,
>-    zero = r0,
>-    at = r1,
>-    v0 = r2,
>-    v1 = r3,
>-    a0 = r4,
>-    a1 = r5,
>-    a2 = r6,
>-    a3 = r7,
>-    t0 = r8,
>-    t1 = r9,
>-    t2 = r10,
>-    t3 = r11,
>-    t4 = r12,
>-    t5 = r13,
>-    t6 = r14,
>-    t7 = r15,
>-    s0 = r16,
>-    s1 = r17,
>-    s2 = r18,
>-    s3 = r19,
>-    s4 = r20,
>-    s5 = r21,
>-    s6 = r22,
>-    s7 = r23,
>-    t8 = r24,
>-    t9 = r25,
>-    k0 = r26,
>-    k1 = r27,
>-    gp = r28,
>-    sp = r29,
>-    fp = r30,
>-    ra = r31,
>+#define REGID(id, nsid, name, r, cs) id,
>+    FOR_EACH_GP_REGISTER(REGID)
>+#undef REGID
>+#define REGALIAS(id, alias) id = alias,
>+    FOR_EACH_REGISTER_ALIAS(REGALIAS)
>+#undef REGALIAS
>     InvalidGPRReg = -1,
> } RegisterID;
> 
> typedef enum : int8_t {
>-    fir = 0,
>-    fccr = 25,
>-    fexr = 26,
>-    fenr = 28,
>-    fcsr = 31,
>-    pc
>+#define REGID(id, nsid, name, idx) id = idx,
>+    FOR_EACH_SP_REGISTER(REGID)
>+#undef REGID
> } SPRegisterID;
> 
> typedef enum : int8_t {
>-    f0,
>-    f1,
>-    f2,
>-    f3,
>-    f4,
>-    f5,
>-    f6,
>-    f7,
>-    f8,
>-    f9,
>-    f10,
>-    f11,
>-    f12,
>-    f13,
>-    f14,
>-    f15,
>-    f16,
>-    f17,
>-    f18,
>-    f19,
>-    f20,
>-    f21,
>-    f22,
>-    f23,
>-    f24,
>-    f25,
>-    f26,
>-    f27,
>-    f28,
>-    f29,
>-    f30,
>-    f31,
>+#define REGID(id, ndsid, name, r, cs) id,
>+    FOR_EACH_FP_REGISTER(REGID)
>+#undef REGID
>     InvalidFPRReg = -1,
> } FPRegisterID;
> 
>@@ -179,46 +92,31 @@ public:
>     {
>         ASSERT(id >= firstRegister() && id <= lastRegister());
>         static const char* const nameForRegister[numberOfRegisters()] = {
>-            "zero", "at", "v0", "v1",
>-            "a0", "a1", "a2", "a3",
>-            "t0", "t1", "t2", "t3",
>-            "t4", "t5", "t6", "t7"
>+#define REGNAME(id, nsid, name, r, c) name,
>+        FOR_EACH_GP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
> 
>     static const char* sprName(SPRegisterID id)
>     {
>-        switch (id) {
>-        case MIPSRegisters::fir:
>-            return "fir";
>-        case MIPSRegisters::fccr:
>-            return "fccr";
>-        case MIPSRegisters::fexr:
>-            return "fexr";
>-        case MIPSRegisters::fenr:
>-            return "fenr";
>-        case MIPSRegisters::fcsr:
>-            return "fcsr";
>-        case MIPSRegisters::pc:
>-            return "pc";
>-        default:
>-            RELEASE_ASSERT_NOT_REACHED();
>-        }
>+        ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
>+        static const char* const nameForRegister[numberOfSPRegisters()] = {
>+#define REGNAME(id, nsid, name, idx) name,
>+        FOR_EACH_SP_REGISTER(REGNAME)
>+#undef REGNAME
>+        };
>+        return nameForRegister[id];
>     }
> 
>     static const char* fprName(FPRegisterID id)
>     {
>         ASSERT(id >= firstFPRegister() && id <= lastFPRegister());
>         static const char* const nameForRegister[numberOfFPRegisters()] = {
>-            "f0", "f1", "f2", "f3",
>-            "f4", "f5", "f6", "f7",
>-            "f8", "f9", "f10", "f11",
>-            "f12", "f13", "f14", "f15"
>-            "f16", "f17", "f18", "f19"
>-            "f20", "f21", "f22", "f23"
>-            "f24", "f25", "f26", "f27"
>-            "f28", "f29", "f30", "f31"
>+#define REGNAME(id, nsid, name, r, cs) name,
>+        FOR_EACH_FP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>diff --git a/Source/JavaScriptCore/assembler/MIPSRegisters.h b/Source/JavaScriptCore/assembler/MIPSRegisters.h
>new file mode 100644
>index 00000000000..6eb10ee687f
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/MIPSRegisters.h
>@@ -0,0 +1,149 @@
>+/*
>+ * Copyright (C) 2019 Metrological Group B.V.
>+ * Copyright (C) 2019 Igalia S.L.
>+ *
>+ * Redistribution and use in source and binary forms, with or without
>+ * modification, are permitted provided that the following conditions
>+ * are met:
>+ * 1. Redistributions of source code must retain the above copyright
>+ *    notice, this list of conditions and the following disclaimer.
>+ * 2. Redistributions in binary form must reproduce the above copyright
>+ *    notice, this list of conditions and the following disclaimer in the
>+ *    documentation and/or other materials provided with the distribution.
>+ *
>+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
>+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
>+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
>+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
>+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
>+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
>+ */
>+
>+#pragma once
>+
>+#define REGNS MIPSRegisters
>+#define n(id) id, REGNS::id
>+#define nn(id) id, REGNS::id, #id
>+
>+#define FOR_EACH_REGISTER(macro)                \
>+    FOR_EACH_GP_REGISTER(macro)                 \
>+    FOR_EACH_FP_REGISTER(macro)
>+
>+#define macro(m, ...) m(__VA_ARGS__)
>+
>+#define FOR_EACH_GP_REGISTER(m)                 \
>+    macro(m, n(r0),  "zero", 0, 0)               \
>+    macro(m, n(r1),  "at",   0, 0)                 \
>+    macro(m, n(r2),  "v0",   0, 0)                 \
>+    macro(m, n(r3),  "v1",   0, 0)                 \
>+    macro(m, n(r4),  "a0",   0, 0)                 \
>+    macro(m, n(r5),  "a1",   0, 0)                 \
>+    macro(m, n(r6),  "a2",   0, 0)                 \
>+    macro(m, n(r7),  "a3",   0, 0)                 \
>+    macro(m, n(r8),  "t0",   0, 0)                 \
>+    macro(m, n(r9),  "t1",   0, 0)                 \
>+    macro(m, n(r10), "t2",   0, 0)                 \
>+    macro(m, n(r11), "t3",   0, 0)                 \
>+    macro(m, n(r12), "t4",   0, 0)                 \
>+    macro(m, n(r13), "t5",   0, 0)                 \
>+    macro(m, n(r14), "t6",   0, 0)                 \
>+    macro(m, n(r15), "t7",   0, 0)                 \
>+    macro(m, n(r16), "s0",   0, 1)                 \
>+    macro(m, n(r17), "s1",   0, 0)                 \
>+    macro(m, n(r18), "s2",   0, 0)                 \
>+    macro(m, n(r19), "s3",   0, 0)                 \
>+    macro(m, n(r20), "s4",   0, 0)                 \
>+    macro(m, n(r21), "s5",   0, 0)                 \
>+    macro(m, n(r22), "s6",   0, 0)                 \
>+    macro(m, n(r23), "s7",   0, 0)                 \
>+    macro(m, n(r24), "t8",   0, 0)                 \
>+    macro(m, n(r25), "t9",   0, 0)                 \
>+    macro(m, n(r26), "k0",   0, 0)                 \
>+    macro(m, n(r27), "k1",   0, 0)                 \
>+    macro(m, n(r28), "gp",   0, 0)                 \
>+    macro(m, n(r29), "sp",   0, 0)                 \
>+    macro(m, n(r30), "fp",   0, 0)                 \
>+    macro(m, n(r31), "ra",   0, 0)
>+
>+#define FOR_EACH_REGISTER_ALIAS(macro)          \
>+    macro(zero, r0)                             \
>+    macro(at,   r1)                             \
>+    macro(v0,   r2)                             \
>+    macro(v1,   r3)                             \
>+    macro(a0,   r4)                             \
>+    macro(a1,   r5)                             \
>+    macro(a2,   r6)                             \
>+    macro(a3,   r7)                             \
>+    macro(t0,   r8)                             \
>+    macro(t1,   r9)                             \
>+    macro(t2,   r10)                            \
>+    macro(t3,   r11)                            \
>+    macro(t4,   r12)                            \
>+    macro(t5,   r13)                            \
>+    macro(t6,   r14)                            \
>+    macro(t7,   r15)                            \
>+    macro(s0,   r16)                            \
>+    macro(s1,   r17)                            \
>+    macro(s2,   r18)                            \
>+    macro(s3,   r19)                            \
>+    macro(s4,   r20)                            \
>+    macro(s5,   r21)                            \
>+    macro(s6,   r22)                            \
>+    macro(s7,   r23)                            \
>+    macro(t8,   r24)                            \
>+    macro(t9,   r25)                            \
>+    macro(k0,   r26)                            \
>+    macro(k1,   r27)                            \
>+    macro(gp,   r28)                            \
>+    macro(sp,   r29)                            \
>+    macro(fp,   r30)                            \
>+    macro(ra,   r31)
>+
>+#define FOR_EACH_SP_REGISTER(m)                    \
>+    macro(m, nn(fir),   0)                         \
>+    macro(m, nn(fccr), 25)                         \
>+    macro(m, nn(fexr), 26)                         \
>+    macro(m, nn(fenr), 28)                         \
>+    macro(m, nn(fcsr), 31)                         \
>+    macro(m, nn(pc),   32)
>+
>+#define FOR_EACH_FP_REGISTER(m)                    \
>+    macro(m, nn(f0), 0, 0)                         \
>+    macro(m, nn(f1), 0, 0)                         \
>+    macro(m, nn(f2), 0, 0)                         \
>+    macro(m, nn(f3), 0, 0)                         \
>+    macro(m, nn(f4), 0, 0)                         \
>+    macro(m, nn(f5), 0, 0)                         \
>+    macro(m, nn(f6), 0, 0)                         \
>+    macro(m, nn(f7), 0, 0)                         \
>+    macro(m, nn(f8), 0, 0)                         \
>+    macro(m, nn(f9), 0, 0)                         \
>+    macro(m, nn(f10), 0, 0)                        \
>+    macro(m, nn(f11), 0, 0)                        \
>+    macro(m, nn(f12), 0, 0)                        \
>+    macro(m, nn(f13), 0, 0)                        \
>+    macro(m, nn(f14), 0, 0)                        \
>+    macro(m, nn(f15), 0, 0)                        \
>+    macro(m, nn(f16), 0, 0)                        \
>+    macro(m, nn(f17), 0, 0)                        \
>+    macro(m, nn(f18), 0, 0)                        \
>+    macro(m, nn(f19), 0, 0)                        \
>+    macro(m, nn(f20), 0, 0)                        \
>+    macro(m, nn(f21), 0, 0)                        \
>+    macro(m, nn(f22), 0, 0)                        \
>+    macro(m, nn(f23), 0, 0)                        \
>+    macro(m, nn(f24), 0, 0)                        \
>+    macro(m, nn(f25), 0, 0)                        \
>+    macro(m, nn(f26), 0, 0)                        \
>+    macro(m, nn(f27), 0, 0)                        \
>+    macro(m, nn(f28), 0, 0)                        \
>+    macro(m, nn(f29), 0, 0)                        \
>+    macro(m, nn(f30), 0, 0)                        \
>+    macro(m, nn(f31), 0, 0)
>+
>+
>diff --git a/Source/JavaScriptCore/assembler/RegisterInfo.h b/Source/JavaScriptCore/assembler/RegisterInfo.h
>new file mode 100644
>index 00000000000..b281dd63497
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/RegisterInfo.h
>@@ -0,0 +1,17 @@
>+#pragma once
>+
>+#include <wtf/Assertions.h>
>+
>+#if CPU(X86)
>+#  include "X86Registers.h"
>+#elif CPU(X86_64)
>+#  include "X86_64Registers.h"
>+#elif CPU(MIPS)
>+#  include "MIPSRegisters.h"
>+#elif CPU(ARM_THUMB2)
>+#  include "ARMv7Registers.h"
>+#elif CPU(ARM64)
>+#  include "ARM64Registers.h"
>+#else
>+    UNREACHABLE_FOR_PLATFORM();
>+#endif
>diff --git a/Source/JavaScriptCore/assembler/X86Assembler.h b/Source/JavaScriptCore/assembler/X86Assembler.h
>index 06cb9e171af..8024ebf6a65 100644
>--- a/Source/JavaScriptCore/assembler/X86Assembler.h
>+++ b/Source/JavaScriptCore/assembler/X86Assembler.h
>@@ -34,11 +34,14 @@
> #include <stdint.h>
> #include <wtf/Assertions.h>
> #include <wtf/Vector.h>
>+#include "RegisterInfo.h"
> 
> namespace JSC {
> 
> inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
> 
>+// If modifying the namespace name, please be sure to modify it as well
>+//   in X86Registers.h and X86_64Registers.h on the macro definition of REGNS     
> namespace X86Registers {
> 
> #if COMPILER(MSVC)
>@@ -47,56 +50,25 @@ namespace X86Registers {
> #define JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE : int8_t
> #endif
> 
>+#define REGID(id, nsid, name, res, cs) id,
>+
> typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
>-    eax,
>-    ecx,
>-    edx,
>-    ebx,
>-    esp,
>-    ebp,
>-    esi,
>-    edi,
>-#if CPU(X86_64)
>-    r8,
>-    r9,
>-    r10,
>-    r11,
>-    r12,
>-    r13,
>-    r14,
>-    r15,
>-#endif
>-    InvalidGPRReg = -1,
>+  FOR_EACH_GP_REGISTER(REGID)
>+  InvalidGPRReg = -1,
> } RegisterID;
> 
> typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
>-    eip,
>-    eflags
>+  FOR_EACH_SP_REGISTER(REGID)                                                     
> } SPRegisterID;
> 
> typedef enum JSC_X86_ASM_REGISTER_ID_ENUM_BASE_TYPE {
>-    xmm0,
>-    xmm1,
>-    xmm2,
>-    xmm3,
>-    xmm4,
>-    xmm5,
>-    xmm6,
>-    xmm7,
>-#if CPU(X86_64)
>-    xmm8,
>-    xmm9,
>-    xmm10,
>-    xmm11,
>-    xmm12,
>-    xmm13,
>-    xmm14,
>-    xmm15,
>-#endif
>-    InvalidFPRReg = -1,
>+  FOR_EACH_FP_REGISTER(REGID)
>+  InvalidFPRReg = -1,
> } XMMRegisterID;
> 
>-} // namespace X86Register
>+#undef REGID
>+
>+} // namespace X86Registers
> 
> class X86Assembler {
> public:
>@@ -137,15 +109,9 @@ public:
>     {
>         ASSERT(id >= firstRegister() && id <= lastRegister());
>         static const char* const nameForRegister[numberOfRegisters()] = {
>-#if CPU(X86_64)
>-            "rax", "rcx", "rdx", "rbx",
>-            "rsp", "rbp", "rsi", "rdi",
>-            "r8", "r9", "r10", "r11",
>-            "r12", "r13", "r14", "r15"
>-#else
>-            "eax", "ecx", "edx", "ebx",
>-            "esp", "ebp", "esi", "edi",
>-#endif
>+#define REGNAME(id, nsid, name, res, cs) name,
>+        FOR_EACH_GP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>@@ -154,11 +120,9 @@ public:
>     {
>         ASSERT(id >= firstSPRegister() && id <= lastSPRegister());
>         static const char* const nameForRegister[numberOfSPRegisters()] = {
>-#if CPU(X86_64)
>-            "rip", "rflags"
>-#else
>-            "eip", "eflags"
>-#endif
>+#define REGNAME(id, nsid, name, res, cs) name,
>+        FOR_EACH_SP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[id];
>     }
>@@ -167,12 +131,9 @@ public:
>     {
>         ASSERT(reg >= firstFPRegister() && reg <= lastFPRegister());
>         static const char* const nameForRegister[numberOfFPRegisters()] = {
>-            "xmm0", "xmm1", "xmm2", "xmm3",
>-            "xmm4", "xmm5", "xmm6", "xmm7",
>-#if CPU(X86_64)
>-            "xmm8", "xmm9", "xmm10", "xmm11",
>-            "xmm12", "xmm13", "xmm14", "xmm15"
>-#endif
>+#define REGNAME(id, nsid, name, res, cs) name,
>+        FOR_EACH_FP_REGISTER(REGNAME)
>+#undef REGNAME
>         };
>         return nameForRegister[reg];
>     }
>diff --git a/Source/JavaScriptCore/assembler/X86Registers.h b/Source/JavaScriptCore/assembler/X86Registers.h
>new file mode 100644
>index 00000000000..44925f3aefe
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/X86Registers.h
>@@ -0,0 +1,71 @@
>+/*
>+ * Copyright (C) 2019 Metrological Group B.V.
>+ * Copyright (C) 2019 Igalia S.L.
>+ *
>+ * Redistribution and use in source and binary forms, with or without
>+ * modification, are permitted provided that the following conditions
>+ * are met:
>+ * 1. Redistributions of source code must retain the above copyright
>+ *    notice, this list of conditions and the following disclaimer.
>+ * 2. Redistributions in binary form must reproduce the above copyright
>+ *    notice, this list of conditions and the following disclaimer in the
>+ *    documentation and/or other materials provided with the distribution.
>+ *
>+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
>+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
>+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
>+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
>+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
>+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
>+ */
>+
>+#pragma once
>+
>+#define REGNS X86Registers
>+#define n(id) id, REGNS::id
>+#define nn(id) id, REGNS::id, #id
>+
>+#if !OS(WINDOWS)
>+
>+#define FOR_EACH_GP_REGISTER(macro)             \
>+    macro(n(eax), "rax", 0, 0)                  \
>+    macro(n(ecx), "rcx", 0, 0)                  \
>+    macro(n(edx), "rdx", 0, 0)                  \
>+    macro(n(ebx), "rbx", 0, 1)                  \
>+    macro(n(esp), "rsp", 0, 0)                  \
>+    macro(n(ebp), "rbp", 0, 1)                  \
>+    macro(n(esi), "rsi", 0, 0)                  \
>+    macro(n(edi), "rdi", 0, 0)
>+
>+#else // OS(WINDOWS)
>+
>+#define FOR_EACH_GP_REGISTER(macro)             \
>+    macro(n(eax), "rax", 0, 0)                  \
>+    macro(n(ecx), "rcx", 0, 0)                  \
>+    macro(n(edx), "rdx", 0, 0)                  \
>+    macro(n(ebx), "rbx", 0, 1)                  \
>+    macro(n(esp), "rsp", 0, 0)                  \
>+    macro(n(ebp), "rbp", 0, 1)                  \
>+    macro(n(esi), "rsi", 0, 1)                  \
>+    macro(n(edi), "rdi", 0, 1)
>+
>+#endif // !OS(WINDOWS)
>+
>+#define FOR_EACH_FP_REGISTER(macro)            \
>+    macro(nn(xmm0), 0, 0)                       \
>+    macro(nn(xmm1), 0, 0)                       \
>+    macro(nn(xmm2), 0, 0)                       \
>+    macro(nn(xmm3), 0, 0)                       \
>+    macro(nn(xmm4), 0, 0)                       \
>+    macro(nn(xmm5), 0, 0)                       \
>+    macro(nn(xmm6), 0, 0)                       \
>+    macro(nn(xmm7), 0, 0)
>+
>+#define FOR_EACH_SP_REGISTER(macro)                \
>+    macro(nn(eip),    0, 0)                        \
>+    macro(nn(eflags), 0, 0)
>diff --git a/Source/JavaScriptCore/assembler/X86_64Registers.h b/Source/JavaScriptCore/assembler/X86_64Registers.h
>new file mode 100644
>index 00000000000..6472512568d
>--- /dev/null
>+++ b/Source/JavaScriptCore/assembler/X86_64Registers.h
>@@ -0,0 +1,97 @@
>+/*
>+ * Copyright (C) 2019 Metrological Group B.V.
>+ * Copyright (C) 2019 Igalia S.L.
>+ *
>+ * Redistribution and use in source and binary forms, with or without
>+ * modification, are permitted provided that the following conditions
>+ * are met:
>+ * 1. Redistributions of source code must retain the above copyright
>+ *    notice, this list of conditions and the following disclaimer.
>+ * 2. Redistributions in binary form must reproduce the above copyright
>+ *    notice, this list of conditions and the following disclaimer in the
>+ *    documentation and/or other materials provided with the distribution.
>+ *
>+ * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
>+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
>+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
>+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL APPLE INC. OR
>+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
>+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
>+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
>+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
>+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
>+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
>+ */
>+
>+#pragma once
>+
>+#define REGNS X86Registers
>+#define n(id) id, REGNS::id
>+#define nn(id) id, REGNS::id, #id
>+
>+#define macro(m, ...) m(__VA_ARGS__)
>+
>+#if !OS(WINDOWS)
>+
>+#define FOR_EACH_GP_REGISTER(m)                 \
>+    macro(m, n(eax), "rax", 0, 0)               \
>+    macro(m, n(ecx), "rcx", 0, 0)               \
>+    macro(m, n(edx), "rdx", 0, 0)               \
>+    macro(m, n(ebx), "rbx", 0, 1)               \
>+    macro(m, n(esp), "rsp", 0, 0)               \
>+    macro(m, n(ebp), "rbp", 0, 1)               \
>+    macro(m, n(esi), "rsi", 0, 0)               \
>+    macro(m, n(edi), "rdi", 0, 0)               \
>+    macro(m, nn(r8),        0, 0)               \
>+    macro(m, nn(r9),        0, 0)               \
>+    macro(m, nn(r10),       0, 0)               \
>+    macro(m, nn(r11),       0, 0)               \
>+    macro(m, nn(r12),       0, 0)               \
>+    macro(m, nn(r13),       0, 0)               \
>+    macro(m, nn(r14),       0, 0)               \
>+    macro(m, nn(r15),       0, 0)
>+
>+#else // OS(WINDOWS)
>+
>+#define FOR_EACH_GP_REGISTER(m)                 \
>+    macro(m, n(eax), "rax", 0, 0)               \
>+    macro(m, n(ecx), "rcx", 0, 0)               \
>+    macro(m, n(edx), "rdx", 0, 0)               \
>+    macro(m, n(ebx), "rbx", 0, 1)               \
>+    macro(m, n(esp), "rsp", 0, 0)               \
>+    macro(m, n(ebp), "rbp", 0, 1)               \
>+    macro(m, n(esi), "rsi", 0, 1)               \
>+    macro(m, n(edi), "rdi", 0, 1)               \
>+    macro(m, nn(r8),        0, 0)               \
>+    macro(m, nn(r9),        0, 0)               \
>+    macro(m, nn(r10),       0, 0)               \
>+    macro(m, nn(r11),       0, 0)               \
>+    macro(m, nn(r12),       0, 0)               \
>+    macro(m, nn(r13),       0, 0)               \
>+    macro(m, nn(r14),       0, 0)               \
>+    macro(m, nn(r15),       0, 0)
>+
>+#endif // !OS(WINDOWS)
>+
>+#define FOR_EACH_FP_REGISTER(m)                 \
>+    macro(m, nn(xmm0),  0, 0)                   \
>+    macro(m, nn(xmm1),  0, 0)                   \
>+    macro(m, nn(xmm2),  0, 0)                   \
>+    macro(m, nn(xmm3),  0, 0)                   \
>+    macro(m, nn(xmm4),  0, 0)                   \
>+    macro(m, nn(xmm5),  0, 0)                   \
>+    macro(m, nn(xmm6),  0, 0)                   \
>+    macro(m, nn(xmm7),  0, 0)                   \
>+    macro(m, nn(xmm8),  0, 0)                   \
>+    macro(m, nn(xmm9),  0, 0)                   \
>+    macro(m, nn(xmm10), 0, 0)                   \
>+    macro(m, nn(xmm11), 0, 0)                   \
>+    macro(m, nn(xmm12), 0, 0)                   \
>+    macro(m, nn(xmm13), 0, 0)                   \
>+    macro(m, nn(xmm14), 0, 0)                   \
>+    macro(m, nn(xmm15), 0, 0)
>+
>+#define FOR_EACH_SP_REGISTER(m)                 \
>+    macro(m, nn(eip),    0, 0)                  \
>+    macro(m, nn(eflags), 0, 0)
>diff --git a/Source/JavaScriptCore/jit/GPRInfo.h b/Source/JavaScriptCore/jit/GPRInfo.h
>index 6bcf676f3c5..a3f87554579 100644
>--- a/Source/JavaScriptCore/jit/GPRInfo.h
>+++ b/Source/JavaScriptCore/jit/GPRInfo.h
>@@ -33,7 +33,7 @@ namespace JSC {
> 
> enum NoResultTag { NoResult };
> 
>-// We use the same conventions in the basline JIT as in the LLint. If you
>+// We use the same conventions in the baseline JIT as in the LLint. If you
> // change mappings in the GPRInfo, you should change them in the offlineasm
> // compiler adequately. The register naming conventions are described at the
> // top of the LowLevelInterpreter.asm file.
>diff --git a/Source/JavaScriptCore/jit/RegisterSet.cpp b/Source/JavaScriptCore/jit/RegisterSet.cpp
>index ed294cb2d9c..bf12f30df0b 100644
>--- a/Source/JavaScriptCore/jit/RegisterSet.cpp
>+++ b/Source/JavaScriptCore/jit/RegisterSet.cpp
>@@ -32,6 +32,7 @@
> #include "JSCInlines.h"
> #include "MacroAssembler.h"
> #include "RegisterAtOffsetList.h"
>+#include "RegisterInfo.h"
> #include <wtf/CommaPrinter.h>
> 
> namespace JSC {
>@@ -45,17 +46,14 @@ RegisterSet RegisterSet::stackRegisters()
> 
> RegisterSet RegisterSet::reservedHardwareRegisters()
> {
>-#if CPU(ARM64)
>-#if PLATFORM(IOS_FAMILY)
>-    return RegisterSet(ARM64Registers::x18, ARM64Registers::lr);
>-#else
>-    return RegisterSet(ARM64Registers::lr);
>-#endif // PLATFORM(IOS_FAMILY)
>-#elif CPU(ARM_THUMB2)
>-    return RegisterSet(ARMRegisters::lr, ARMRegisters::pc);
>-#else
>-    return { };
>-#endif
>+    RegisterSet result;
>+
>+#define SET_IF_RESERVED(id, nsid, name, r, cs) if (r) result.set(nsid);
>+    FOR_EACH_GP_REGISTER(SET_IF_RESERVED)
>+    FOR_EACH_FP_REGISTER(SET_IF_RESERVED)
>+#undef SET_IF_RESERVED
>+     
>+    return result;
> }
> 
> RegisterSet RegisterSet::runtimeTagRegisters()
>@@ -111,53 +109,12 @@ RegisterSet RegisterSet::macroScratchRegisters()
> RegisterSet RegisterSet::calleeSaveRegisters()
> {
>     RegisterSet result;
>-#if CPU(X86)
>-    result.set(X86Registers::ebx);
>-    result.set(X86Registers::ebp);
>-    result.set(X86Registers::edi);
>-    result.set(X86Registers::esi);
>-#elif CPU(X86_64)
>-    result.set(X86Registers::ebx);
>-    result.set(X86Registers::ebp);
>-#if OS(WINDOWS)
>-    result.set(X86Registers::edi);
>-    result.set(X86Registers::esi);
>-#endif
>-    result.set(X86Registers::r12);
>-    result.set(X86Registers::r13);
>-    result.set(X86Registers::r14);
>-    result.set(X86Registers::r15);
>-#elif CPU(ARM_THUMB2)
>-    result.set(ARMRegisters::r4);
>-    result.set(ARMRegisters::r5);
>-    result.set(ARMRegisters::r6);
>-    result.set(ARMRegisters::r8);
>-#if !PLATFORM(IOS_FAMILY)
>-    result.set(ARMRegisters::r9);
>-#endif
>-    result.set(ARMRegisters::r10);
>-    result.set(ARMRegisters::r11);
>-#elif CPU(ARM64)
>-    // We don't include LR in the set of callee-save registers even though it technically belongs
>-    // there. This is because we use this set to describe the set of registers that need to be saved
>-    // beyond what you would save by the platform-agnostic "preserve return address" and "restore
>-    // return address" operations in CCallHelpers.
>-    for (
>-        ARM64Registers::RegisterID reg = ARM64Registers::x19;
>-        reg <= ARM64Registers::x28;
>-        reg = static_cast<ARM64Registers::RegisterID>(reg + 1))
>-        result.set(reg);
>-    result.set(ARM64Registers::fp);
>-    for (
>-        ARM64Registers::FPRegisterID reg = ARM64Registers::q8;
>-        reg <= ARM64Registers::q15;
>-        reg = static_cast<ARM64Registers::FPRegisterID>(reg + 1))
>-        result.set(reg);
>-#elif CPU(MIPS)
>-    result.set(MIPSRegisters::s0);
>-#else
>-    UNREACHABLE_FOR_PLATFORM();
>-#endif
>+
>+#define SET_IF_CALLEESAVED(id, nsid, name, r, cs)  if(cs) result.set(nsid);
>+    FOR_EACH_GP_REGISTER(SET_IF_CALLEESAVED)
>+    FOR_EACH_FP_REGISTER(SET_IF_CALLEESAVED)
>+#undef SET_IF_CALLEESAVED
>+        
>     return result;
> }
>

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Attachments on bug 198604: 371485 | 371498 | 371525 | 371526 | 371583 | 371727 | 371729 | 371733 | 371940 | 371943 | 371945 | 371956 | 372029 | 372049 | 372051 | 372912 | 373008 | 373385